;buildInfoPackage: chisel3, version: 3.4.1, scalaVersion: 2.12.12, sbtVersion: 1.3.10
circuit GCD : 
  module GCD : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<16>, flip b : UInt<16>, flip load : UInt<1>, out : UInt<16>, valid : UInt<1>}
    
    reg x : UInt, clock @[gcd.scala 13:16]
    reg y : UInt, clock @[gcd.scala 14:16]
    when io.load : @[gcd.scala 15:18]
      x <= io.a @[gcd.scala 16:10]
      y <= io.b @[gcd.scala 16:21]
      skip @[gcd.scala 15:18]
    else : @[gcd.scala 17:16]
      node _T = gt(x, y) @[gcd.scala 18:15]
      when _T : @[gcd.scala 18:18]
        node _T_1 = sub(x, y) @[gcd.scala 19:18]
        node _T_2 = tail(_T_1, 1) @[gcd.scala 19:18]
        x <= _T_2 @[gcd.scala 19:14]
        skip @[gcd.scala 18:18]
      else : @[gcd.scala 20:25]
        node _T_3 = leq(x, y) @[gcd.scala 20:21]
        when _T_3 : @[gcd.scala 20:25]
          node _T_4 = sub(y, x) @[gcd.scala 21:18]
          node _T_5 = tail(_T_4, 1) @[gcd.scala 21:18]
          y <= _T_5 @[gcd.scala 21:14]
          skip @[gcd.scala 20:25]
      skip @[gcd.scala 17:16]
    io.out <= x @[gcd.scala 25:17]
    node _T_6 = eq(y, UInt<1>("h00")) @[gcd.scala 26:21]
    io.valid <= _T_6 @[gcd.scala 26:17]
    
